A single event upset (SEU) is the result of an ion transitioning through a semiconductor structure and depositing charge on a critical circuit node within that structure. In a CMOS logic circuit, this can cause an unintended switch in the logic state, creating potentially catastrophic consequences for the system. In the case of storage cells, the primary SEU problem lies in the feedback path, where amplification and feedback of noise on a critical node can permanently change the cell's logic state.
Known SEU hardening techniques for CMOS logic include the use of redundant circuit paths, and for storage cells it is known to use cross-coupled resistors or capacitors. Dual circuit paths provide redundancy and allow implementation of voting schemes to reduce the effect of SEUs. The addition of cross-coupled resistors and capacitors in a storage cell slows the cell's ability to latch false data. However, each of these techniques has its drawbacks. The typical voting scheme uses digital logic to recombine the redundant paths, and thereby actually provides amplification of the SEU. The addition of cross-coupled resistors and capacitors in a storage cell involves more complicated fabrication processes and results in slower response to all input signals, thereby decreasing its operating speed.